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IST, Interconnect Stress Test (PCB Reliability Test)  
 

    

History of IST

  •     1989 Initiated Development at Digital Equipment Corp. – Canada                  

  •     1994 Patents Awarded for Method and Coupon Design

  •     1995 PWB Interconnect Solutions Incorporated

  •     1996 First Systems Installed in North America

  •     1998 First Systems Installed in Asia/Europe

  •     2000 IPC Approval Received (TM 650, Method Number 2.6.26)

  •     2002 Generic Design/Testing/Reporting Strategy Developed

  •     2003 68 IST Machines in the Field – Test Services Expanded

  •     2004 Increase Capability in Analysis of Material with TMA and DMA

  •     Present – Focus on Lead Free + Statistical and Prediction Tools  

     

General Theory

     The IST test system applies a DC current to PWB test vehicles internal and external interconnect, monitoring and controlling the   resistance/temperature throughout each cycle.  The PTH interconnect is generally heated to temperatures above the glass transitional (Tg) of the base material (e.g. 150C +/- 3C in 3 minutes)

     Differential thermal expansion is created and continues throughout testing until failure inception initiates as micro-structure cracking, located in specific regions within one or both interconnects.  Cycling continues until one of the specified rejection criteria is achieved. Coupon rejection can be based on a maximum number of cycles or percentage increases in PTH/Post interconnect elevated resistance.

Other related Information

              About IST  IST History.pdf

              IPC Standard TM2626-Jan2000.PDF

              Application Note Sun Microsystems.pdf

 

 
       
 

 

Asia Qtech Instrument Inc
4F-B, No 327, Sec. 1, Tiding Blvd., Neihu District, Taipei, Taiwan
Tel:+886-2-27966289 Fax:+886-2-27956098